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Possibility analysis of Huawei and Chinese Academy of Sciences developing mask aligner.
Seeing unofficial news, Huawei cooperated with Chinese Academy of Sciences to develop 8nm mask aligner. The reliability and technical possibility of this information are analyzed as follows.

1. Brief Introduction of Chip Manufacturing Process

First, briefly explain the process of chip manufacturing, so that everyone can understand the following technical terms. If you understand this process, you can skip to the second reading.

Here, the wafer manufacturing and sealing and testing links unrelated to the theme are skipped.

You can imagine the process of carving a stamp Suppose we want to carve a stamp with yin (corresponding to yang) (the words are concave and the background is convex, so we need to deduct the strokes of the words), with the above two words: "Renyi". The following example is to illustrate the manufacturing method of the chip, so it is not so troublesome to really engrave the seal. The steps are roughly as follows: 1. Design: Design the words to be engraved on the paper. 2. lettering: use a carving knife to carve the strokes of a word. This paper is called font. 3. Strengthen the lettering surface of the seal (there is no such step in the actual carving of the seal). 4. Paint: coat a layer of paint on the sealing substrate. 5. typesetting: copy typesetting on the drawing (spread typesetting on the drawing and draw strokes). 6. Character display: remove the pigment covered by Chinese characters and strokes, leaving the pigment without strokes. At this time, the unpainted part of the seal shows the word "benevolence and righteousness" (the problem of mirror image inversion is ignored here). 7. lettering, that is, engraving the unpainted part with a carving knife. 8. Remove the paint and wash off the remaining paint.

The steps of making chips correspond to the above steps of carving paper one by one (other steps irrelevant to the content of this paper, such as substrate polishing and multiple cleaning steps, are omitted). ): 1. Chip layout/wiring design (equivalent to design). 2. Making a mask, that is, making a layout pattern mask according to the design (equivalent to carving). 3. Wafer surface oxidation (equivalent to seal lettering surface treatment) 4. Glue coating, that is, coating photoresist on the substrate (equivalent to painting). 5. Photolithography, that is, using light to irradiate the photoresist through the mask plate (equivalent to font reproduction). A mask aligner is used in this step. 6. Development, that is, removing a part of the photoresist irradiated by light (equivalent to development). 7. Etching, that is, removing the oxide film on the wafer surface to expose the high-purity silicon below (equivalent to lettering). 8. Debonding, that is, cleaning the residual photoresist on the wafer surface (equivalent to paint stripping).

The effect of lithography is that the pattern of the silicon dioxide film on the surface of the silicon wafer is completely consistent with the mask, which is equivalent to transferring the pattern on the mask to the silicon dioxide on the surface of the silicon wafer, so that there are countless skylights on the surface of the silicon dioxide that are completely consistent with the mask to prepare for the subsequent process, just like copying the silicon dioxide film with the same pattern as the mask in batches and sticking it on the surface of the silicon wafer.

There is another step in chip manufacturing: doping, that is, different metal ions are implanted into the silicon substrates under countless skylights with different processes, so that these regions change their characteristics and form the required semiconductor electrical properties (that is, a P-type or N-type semiconductor is formed, and a unidirectional P/N junction is formed between two different semiconductor micro-regions, and three continuous PNP or NPN regions contain two P/N junctions to form a triode with amplification effect, which is the most basic element of an integrated circuit).

It should be pointed out that VLSI chips are extremely complex and require dozens of steps. Step 1 only needs once for a chip, and step 2 only needs once, but each step needs to be masked differently. Steps 3 to 8 need to be repeated dozens of times, once for each process, using different masks each time. The specific steps of different processes may be very different, such as wiring process, but photolithography steps are always needed.

Secondly, the difficulty of mask aligner R&D and chip cost.

Mask aligner has tens of thousands of parts, the most important of which are three parts: EUV light source, lens group and high alignment precision worktable. If the problems in these three parts can be solved, the key problems in other parts may not be so difficult to overcome. Those who understand these problems can go directly to the third grade.

Several key factors affecting the output, production efficiency and final product cost of mask aligner;

1.power of euv light source. The greater the power of the light source, the higher the production efficiency. Because according to the wafer area (usually measured by diameter, usually 5, 8, 12 inch) and the size of a single chip, a wafer can arrange dozens to hundreds of chips. Generally, the mask covers only one chip, and each chip on the wafer needs to be exposed once in a process. If a wafer is arranged with 500 chips, a single process needs 500 exposures. When the photosensitive sensitivity of photoresist is constant, the time required for a single chip to be fully exposed in one process depends on the output power or light intensity of mask aligner. The higher the output power, the shorter the exposure time and the higher the production efficiency.

The field of view and luminous efficiency of EUV light source are skipped here.

2. Optical aberration of lens group. When light passes through a lens, it diverges. The most obvious example is that the edge divergence is very obvious when imaging with a super wide-angle lens. Many factors may lead to differences. If the divergence is too large, the pattern projected onto the photoresist through the mask will also diverge accordingly, resulting in a decrease in yield.

3. Positioning accuracy of moving workpiece table. Because a single chip needs multiple exposures, in order to expose multiple chips on a wafer, firstly, the interval between adjacent chips must be accurate, and secondly, each exposure of the same chip must be accurately aligned with the previous exposure position. The poor positioning accuracy of the worktable will lead to the decline of yield, which is one of the main factors that determine the yield.

4. The moving speed of the workpiece table. The total time required for chip exposure is the time for the workbench to move to the chip position and complete positioning plus the simple exposure time. Therefore, the faster the moving and positioning speed, the higher the production efficiency. This index and positioning accuracy contradict each other.

The yield and efficiency of the production line are finally reflected in the final chip cost.

The processing time of other equipment on the wafer production line is calculated according to the wafer. For example, in a single doping process, all chips on the whole wafer are processed at one time. However, the lithography process is calculated according to the number of chips on the wafer, that is, the total time required for the wafer exposure process is the positioning of a single chip plus the exposure time multiplied by the number of chips on the wafer. Therefore, a wafer production line has more mask aligner than other equipment, and the lower the mask aligner efficiency, the more mask aligner the production line needs. Therefore, the efficiency of photoresist affects the production line cost and operating cost. Finally, the increased production line cost due to the inefficient mask aligner also increases the capital occupation and operating cost of the chip.

Thirdly, analyze the real surname of news.

If this news is made up, why not make up 7nm, but make up 8nm that everyone is not used to watching? This is circumstantial evidence, but it is difficult. Besides, it can only be analyzed from a technical point of view.

The domestic workbench seems to have been tested before. It is said that the alignment accuracy can reach several nm, and 8nm mask aligner is enough, but the movement speed index (directly related to production efficiency) is not clear, perhaps worse than the highest level abroad, and the cost of a single product is nothing more than higher.

In fact, EUV light sources are also available in China, but the power is far from enough. The result is that the exposure time required is too long. One is that supporting photoresist is more sensitive and difficult. The other is seriously affecting production efficiency. I don't know how to solve it. Personally, I think the power of the light source can be improved, but it can't reach the usable level (for example, only one exposure can be completed in one minute or several minutes after improvement). Then it may be a feasible way to connect multiple EUV light sources in parallel, but even so, it may still not reach the exposure efficiency level of asml.

The key of the lens is high precision, otherwise the distortion of the mask pattern projected on the chip will be too great, especially around the lens. There may be a breakthrough in high-precision lens processing technology, but if it does not reach the ideal level, it will affect the imaging light field area (the edge can not be used because of divergence) and product yield.

Closer focal length can improve the imaging quality, but the intensity of the same euv light source decreases at closer focal length, which increases the exposure time and reduces the production efficiency.

Therefore, in the past, the EUV lithography technology in China was not realized, but the technical level was not up to standard, and the efficiency and yield of mask aligner used in mass production could not compete with those of ASML products (there was also the problem of small field of view, so it was omitted).

Mask aligner, with low production efficiency and yield, can solve the problem that Huawei has no chips and save its life. Then these two problems that affect the cost of chips seem to be tolerable for Huawei, because survival is the most important thing.

But there is another factor: Huawei has secretly developed many technologies, which were locked in safes before, and some were taken out one after another after being sanctioned. What are the specific ones and how many are not clear to the outside world. You never know what Huawei will take out of its pocket next moment.

For example, a technology disclosed by Huawei mobile phone: computational optics. The algorithm is used to compensate the lens change and correct the pixel position, brightness and color of the photo data according to the known lens change after imaging. Personally, Huawei may use this technology in mask aligner. If the lens is not good, it will use the algorithm to analyze the divergence of this specific lens, then analyze where the divergence occurs, and then fine-tune (polish) the specific position of one or several lenses, and repeat it many times to achieve better results. In this way, the processing cost of lens group will be greatly increased, but at present Huawei can accept it.

There is a similar idea, which is to make an active divergence mask according to the specific divergence characteristics of the lens group to offset the optical divergence generated by the lens group, so that the pattern projected onto the photoresist plane through the mask is less divergent. I don't know how difficult this idea is. EDA software may be required to generate the design of distortion compensation mask according to specific distortion data, or separate software may be required to generate distortion correction mask data with the output of EDA as input.

This is what we know, and there may be other black technologies.

For example, is it possible that Huawei has come up with black technology, and the rumored mask aligner has adopted a completely different technical route from that of ASML, which can greatly simplify the realization of mask aligner? Doing so can also avoid many patent barriers.

Like an X-ray mask aligner? Its shorter wavelength is more conducive to improving the process. When producing high-tech mobile phone chips, other conditions are the same (photoresist sensitivity, mask aligner output power, chip product manufacturing process, etc. ), the production efficiency of X-ray mask mask aligner with shorter wavelength is twice as high as that of EUV light source. Because the wavelength is shorter, X-ray mask aligner does not need the repeated exposure times of chips with higher manufacturing process than EUV mask aligner, so the number of processes can be greatly reduced and the production efficiency can be improved.

The problem is that X-rays penetrate the surname very strongly, and it is not difficult to make masks. Maybe we can only try lead alloy. There is also the problem of X-ray focusing. Ordinary optical lenses can't work, so we should adopt new methods. Fortunately, this X-ray focusing method appeared in 199 1, which was used for radiotherapy equipment at that time, and now the patent at that time has expired. And the output power of the X-ray tube and its focusing optical path. X-ray sensitive photoresist is also brand new.

The technical route of this X-ray mask aligner is completely different from the existing mask aligner in ASML. If the related technical problems can be solved, then China can directly enter the next generation of mask aligner, and mask aligner will no longer be the main limiting factor for process improvement.

Another possibility is to use the hollow glass capillary tube bundle invented by American scientists to focus X-rays to focus extreme ultraviolet light. This method is used for mask aligners without optical lenses.

So personally, I think it is possible to develop 8nm mask aligner now, but it is still surprising that it is so fast, or the credibility seems to be very low for me. However, it is said that SMIC undertakes the verification of the equipment and materials needed for domestic chips. If the 8nm mask aligner really comes out now, it should be verified by SMIC, which will take about one year (longer than mature products). It will take another year to find out whether it is true or not.

I have gained a lot of knowledge from Dr. @ Jim's series of articles on mask aligner, and I just want to express my gratitude here.

Originality is not easy, thank you for your support.