Like ASIC, vendors need to meet the challenges of area and speed in FPGA design. With the increasing number of gates, FPGA needs larger area and size to adapt to more applications, and design tools need to adopt better algorithms to use the area more effectively. The continuous evolution of FPGA technology has also brought a series of new challenges to designers, and the utilization rate of power consumption is one of them, which is an urgent problem to be solved in designing embedded systems based on FPGA for handheld or portable devices.
FPGA in embedded system
A typical embedded system consists of standard interfaces such as processor, memory, USB, SPI and I2C, and peripherals such as LCD and audio output. The core of the device is still the processor and the processor interface, which are connected to various peripherals through on-board wiring. System performance mainly depends on the performance of the processor, and the processor usually has a very standard architecture, so it is not easy to customize.
Sometimes, the processor may be busy processing information from low-speed peripherals. Although the utilization rate of the processor may reach 100% in this case, it is not doing a transaction centered on the microprocessor, but working at a particularly low performance level. Regardless of its core frequency, the microprocessor must wait for data from the low-speed clock. This will also lead to higher power consumption because the utilization rate of the processor is 100%. In this way, the battery life will be shortened, and a larger radiator or fan will be needed to dissipate heat, which will ultimately affect the reliability of the whole system.
Therefore, FPGA plays an important role in this respect, because they can unload many peripheral interactive tasks from the processor. As shown in figure 1, the embedded distribution system of uncompressed audio and video data stream is realized by using standard gigabit TCP/IP network. It has a dedicated DSP processor, which is connected to the FPGA of Xilinx through a standard bus interface, and the FPGA is connected to various low-speed peripherals.
Figure 1: FPGA architecture of audio/video distribution system.
As a startup development kit, the FPGA is connected with 12-bit PCM audio input and 12-bit PCM audio output through I2S interface. It is also connected with video encoder and decoder, and communicates with I2C slave devices and RS232 devices. There are few general-purpose I/O connections to FPGA. The standard bus connecting the processor works at a high speed of 66MHz, and the audio peripheral works at a low speed of 1. 182 MHz. UART and I2C serial interfaces work at 56.6kHz and 100kHz respectively. Since data transmission occurs in multiple clock domains, only the processor can configure the data flow.
In this case, the processor no longer interacts with the low-speed peripherals, but the FPGA reads the data from the low-speed PCM ADC audio device and stores the data in the internal cache of the FPGA. The processor can read data from the cache periodically, or when there is enough data in the cache, the FPGA will send an interrupt to the processor. In this way, the processor has more time to perform the necessary work centered on the processor, and enters the sleep mode when it is idle.
Power consumption problem
In battery-powered embedded systems, energy saving is the most important consideration. Power consumption can be divided into three categories: startup power consumption, static power consumption and dynamic power consumption. The designer can't control the startup power consumption, which plays an important role in determining the power supply selection. Most maximum current values refer to the values reached at this stage. However, static power consumption and dynamic power consumption are two different fields. Through reasonable planning and the following correct guiding principles, embedded designers using FPGA can make remarkable progress in power optimization.
Static power consumption refers to the power consumption generated when there is still current flowing through components when the system is not working, which is generally caused by device bias current and leakage current. Static power consumption also depends on the operating voltage. Reducing the operating voltage can reduce the static power consumption, but this strategy is not always in the hands of designers. What designers can do is to define a reasonable architecture, under which they need to use the least resources, and at the same time use the resources as much as possible to use FPGA modules in the most efficient way.
Another technology to reduce static power consumption is to estimate power consumption early in the design cycle, change the topology or use different IP modules. For example, Xilinx's xPower Estimator tool is very useful at this time, and you can know whether the design meets the power consumption budget at an early stage. The previous power consumption estimation may not be completely accurate, but it is really helpful as a guiding tool.
Dynamic power consumption is caused by some behaviors of FPGA gates (such as signal switching). When the two gates are temporarily turned on, current and capacitance will be generated. The speed of signal switching determines the power consumption. Another factor affecting dynamic power consumption is the inherent capacitance formed in the internal structure of the circuit. Dynamic power consumption is a function of clock frequency, the number of gates being switched and the switching rate of these gates. The capacitive load on the outlet and wiring of the door leaf will increase the dynamic power consumption, which is proportional to the product of capacitance, voltage and frequency square.
Designers have the greatest control over this power consumption, and they can use many technologies to achieve the maximum improvement of dynamic power consumption. Reducing the signal switching frequency can reduce the power consumption exponentially. As shown in figure 1, the control logic, parity or frame overflow errors of UART all occur in the low-speed clock domain. Even if the number of gates does not decrease, the power consumption will decrease. Designers can also reduce dynamic power consumption by lowering the overall operating frequency (if feasible). For example, after feasibility and performance analysis, the designer decided that the above design can work not only at 133MHz, but also at 66MHz. DSP supports these two rates, and reducing voltage also helps to reduce power consumption.
Another technique is to reduce the number of active gates in the working mode. Sometimes a part of the logic is opened and configured at startup, but nothing is really needed. For example, the analog audio capture unit is working, but the device is not performing any digital SPDIF audio capture. In this case, the general digital SPDIF audio capture circuit will still perform data sampling, biphase decoding and other work, resulting in unnecessary power consumption waste. If the whole digital SPDIF audio capture circuit is disabled, so that there is no signal switching action in the circuit, the dynamic power consumption will be significantly reduced.
Designers can disable the clock transmitted to this part of the circuit to achieve this goal. A simple method is to AND the clock signal and the enable signal, as shown in Figure 2. If the enable signal is low, the output of the AND gate will remain low. If the enable signal is high, the AND gate outputs a clock signal.
Figure 2: A simple clock gating mechanism.
Other methods can also be used. If possible and supported by topology, the number of signal lines can be reduced by multiplexing addresses and data lines. In our example, the output of the video encoder is 16 bit data, which can be multiplexed into 8 bits and then sent out at two edges (rising edge and falling edge) of the clock respectively. Doing so can also save dynamic power consumption. In addition, choosing serial interface instead of parallel interface can also reduce power consumption. LVTTL or LVCMOS I/O with low capacitive load is also useful.
Embedded processor
Embedding processor into FPGA is another strategy that handheld device designers can adopt, which can bring many benefits. First of all, the above challenges brought by customizing the processor are reduced. Secondly, the interaction between peripherals and processors takes place inside FPGA, so the number of I/O can be reduced. Because I/O consumes a lot of power, it can also achieve a certain degree of energy saving effect. The Virtex-5 version of Xilinx supports PowerPC 440 processor, hard processor and MicroBlaze soft processor, which designers can use to create high-end or low-end application systems.
With the invention of 90m and 65nm semiconductor technology, the size of gate is shrinking, which leads to the problem of static power consumption becoming more and more prominent. Today, it is more and more sensitive to power consumption indicators, which is a very challenging phenomenon. Because power consumption has attracted the attention of many FPGA vendors, many exciting new technologies have emerged in this field. Low power design will determine how strong the integration ability of a system is, and the industry urgently needs to standardize the design technology that pays attention to power consumption.