What is the code 66 displayed on the test card?

Computer motherboard fault diagnosis card code comparison table

00. Configuration of display system; Boot the control INI 19. .

0 1 processor test 1, processor status verification, if the test fails, the loop is infinite. The test of processor registers is about to begin, and unmasked interrupts are about to be disabled. The CPU register test is in progress or failed.

Determine the type of diagnosis (normal or manufacturing). If the keyboard buffer contains data, it will be invalid. Disable non-maskable interrupts; Start with procrastination. CMOS write/read is in progress or has failed.

03 Clear the 8042 keyboard controller, and the power-on delay of issuing the TESTKBRD command (AAH) has been completed. ROM BIOS checks whether the component is running or faulty.

Reset the 8042 keyboard controller and verify TESTKBRD. Soft reset/power-on test of keyboard controller. The test of the programmable interval timer is in progress or fails.

If the manufacturing test 1 to 5 is repeated continuously, the control state of 8042 can be obtained. Determining soft reset/power-on; Is about to begin. DMA preparation is in progress or failed.

Make initial preparations for circuit chips, disable video, parity and DMA circuit chips, and clear DMA circuit chips, all page registers and CMOS stop bytes. ROM has started to calculate the ROM BIOS checksum and check whether the keyboard buffer is cleared. DMA initial page register read/write test is in progress or failed.

07 processor test 2, verify the operation of CPU registers. ROM BIOS checksum is normal, keyboard buffer has been emptied, and BAT (basic guarantee test) command is issued to the keyboard. .

Make initial preparation for CMOS timer and update the timer normally. The BAT command has been downloaded to the keyboard, and the BAT command will be written soon. RAM update check is in progress or has failed.

The sum of EPROM check must be equal to zero before passing. Verify the basic guarantee test of the keyboard, and then verify the keyboard command bytes. The first 64K memory test is in progress.

Make preliminary preparations for the video interface. Issue keyboard command byte code and write command byte data. The first 64K RAM chip or data line fails and shifts.

Test 8254 channel 0. Write the command byte of keyboard controller, and the lock/unlock command of pins 23 and 24 will be issued soon. The first 64K RAM odd/even logic failed.

Test channel 8254 1. Keyboard controller pins 23 and 24 have been locked/unlocked; NOP command has been issued. The address line of the first 64K RAN is faulty.

0D 1。 Check whether the CPU speed matches the system clock. 2. Check whether the programmed value of the control chip meets the initial setting. 3. Test the video channel. If you fail, honk the horn. NOP command has been processed; Then test the CMOS stop register. Parity check of the first 64K RAM failed.

Test CMOS power-off bytes. CMOS stop register read/write test; CMOS checksum will be calculated. Initialize the input/output port address.

0F test extended CMOS. The calculated CMOS checksum is written into the diagnostic byte; CMOS begins initial preparation. .

10 test DMA channel 0. CMOS has made preliminary preparations, and the date and time of CMOS status register are about to be prepared. The first 64K RAM bit 0 failed.

Test DMA channel 1. The CMOS status register is initially prepared to disable DMA and interrupt controller. The first 64DK RAM bit 1 failed.

12 test DMA page register. Deactivate DMA controller 1 and interrupt controller 1 and 2; That is, the video display and port B are initially prepared. The second bit of the first 64DK RAM failed.

13 Test the 874 1 keyboard controller interface. Video surveillance has been disabled, and port B has been preliminarily prepared; Circuit chip initialization/automatic memory detection is about to begin. The third bit of the first 64DK RAM failed.

14 Test the memory update trigger circuit. Circuit chip initialization/automatic detection of storage end; The 8254 timer test is about to begin. The 4th bit of the first 64DK RAM failed.

15 Test the system memory starting with 64K. Channel 2 timer has been tested halfway; The 8254 Channel 2 timer is about to complete the test. The 5th bit of the first 64DK RAM failed.

16 Establish the interrupt vector table used by 8259. End of channel 2 timer test; The 8254 channel 1 timer is about to complete the test. The 6th bit of the first 64DK RAM failed.

17 calibrates the video input/output operation, and enables the video BIOS if it is installed. 1 End of channel timer test; The 8254 channel 0 timer is about to complete the test. The 7th bit of the first 64DK RAM failed.

18 test memory. If the selected video BIOS is installed, it can be bypassed. End of channel 0 timer test; Updating memory is about to begin. The first 64DK RAM bit 8 failed.

Mask bit of interrupt controller (8259) of 19 test channel 1. The update of the memory has started, and then the update of the memory will be completed. The 9th bit of the first 64DK RAM failed.

1A Test the mask bit of the interrupt controller (8259) in channel 2. The memory update line is being triggered, and the on/off time of 15 microseconds is about to be checked. The first 64DK RAM bit 10 failed.

1B test CMOS battery level. Complete the memory refresh time test of 30 microseconds; The basic 64K memory test is about to begin. The first 64DK RAM bit 1 1 failed.

1C test CMOS checksum. The first 64DK RAM bit 12 failed.

1D sets the CMOS configuration. The first 64DK RAM bit 13 failed.

1E measures the size of the system memory and compares it with the CMOS value. The first 64DK RAM bit 14 failed.

1F tests 64K memory with a maximum of 640K. The first 64DK RAM bit 15 failed.

Measure the fixed 8259 interrupt bit. Start the basic 64K memory test; The address line is about to be tested. The slave DMA register test is in progress or failed.

2 1 Maintain NMI bits (parity of input/output channels). Pass the address line test; Parity is about to be triggered. The main DMA register test is in progress or failed.

Test the interrupt function of 8259. End trigger parity; The serial data read/write test will begin. The main interrupt mask register test is in progress or failed.

Test protection mode, 8086 virtual mode and 8086 page mode. The basic 64K serial data reading and writing test is normal; Any adjustment before the interrupt vector is initialized will begin. The slave interrupt mask memory test is in progress or failed.

Measure the extended memory above 1MB. Any adjustment before vector initialization is completed, and the initial preparation of interrupt vector is about to begin. Set the ES segment address register registry to the high end of the memory.

Test all memory except the first 64K. Complete that initial preparation of the interrupt vector; The input/output port of 8042 will be read intermittently for rotation. Loading interrupt vector is in progress or failed.

26 exceptions to test protection methods. Read out the input/output port of 8042; The global data was originally prepared for the intermittent start of rotation. Open the A20 address line; Make it participate in addressing.

Determine the control or mask RAM of the cache. The initial preparation of all 1 data is completed; Any initial preparation after the interrupt vector will follow. Keyboard controller test is in progress or failed.

Determine the cache controller or dedicated 8042 keyboard controller. Initial preparation after completing the interrupt vector; Monochrome mode is about to be adjusted. CMOS power failure/checksum calculation is in progress.

29. The monochrome mode has been adjusted, and the color mode will be adjusted soon. The validity check of CMOS configuration is in progress.

2A Make preliminary preparations for the keyboard controller. The color mode has been set, and the trigger parity before the ROM test is about to be carried out. Clear 64K basic memory.

2B Make initial preparations for disk drives and controllers. Triggering the end of parity check; Any adjustments required before checking the optional video ROM will be controlled. Screen memory test is in progress or failed.

2C Check the serial port and make initial preparations. Complete the processing before the video ROM control; You will view and control the optional video ROM. Initial screen preparation is in progress or there is a failure.

2D detect the parallel port and make initial preparation. The optional video ROM control has been completed, and the control of any other processing after the video ROM recovery control is about to be executed. The screen retrace test is in progress or has failed.

2E Make preliminary preparations for hard disk drive and controller. Recover from the processing after video rom control; If EGA/VGA cannot be found, the display memory read/write test will be performed. Detecting video ROM.

2F Detect the math coprocessor and make preliminary preparations. Unable to find EGA/VGA；; The monitor memory read/write test is about to begin. .

Establish basic memory and expand memory. Pass the display memory read/write test; Scanning inspection is about to take place. I think the screen is working properly.

3 1 Check the selected ROM from C800: 0 to EFFF: 0, and make initial preparations. The display memory read/write test or scan check failed, and another display memory read/write test is about to be conducted. Monochrome display can work.

I/O chips such as COM/LTP/FDD/sound devices on the motherboard are programmed to suit the set values. Pass another display memory read/write test; But another kind of monitor scanning inspection will be carried out. The color display (40 columns) can work.

33. The video surveillance inspection is over; The adjustment switch and the actual card will be used to check the closing type of the display. The color display (80 columns) can work.

34. The monitor adapter has been verified; Then the display mode will be adjusted. The timer tick interrupt test is in progress or has a fault.

35. Finish setting the display mode; The data area of the BIOS ROM will be checked. The shutdown test is in progress or fails.

36. The BIOS ROM data area has been checked; Set the cursor for the boot information. A-20 in the gate circuit is out of order.

37. The cursor setting for identifying the boot information has been completed; The power-on information will be displayed soon. Unexpected interruption in protected mode.

38. Complete the display of boot information; The new cursor position is about to be read. RAM test in progress or address failure > > FFFFH.

39. The saved cursor position has been read, and the reference information string will be displayed soon. .

3A。 The display of the reference information string ends; The discovery information will be displayed soon. Interval timer channel 2 has been tested or failed.

3B The auxiliary cache was originally prepared with an OPTI circuit chip (only 486). Display discovery < < ESC > > information; Virtual mode, memory test is about to begin. The daily calendar clock test is in progress or faulty.

3C establishes a flag that allows access to CMOS settings. Serial port test is in progress or failed.

3D Initialize the keyboard //PS2 mouse //PNP device and the total memory node. Parallel port test is in progress or failed.

3E attempted to open L2 cache. Math coprocessor test is in progress or failed.

40. Preparations for the virtual mode test have begun; Will be checked from the video memory. Adjust the CPU speed to accurately match the peripheral clock.

4 1 interrupt has been turned on, and data will be initialized to facilitate 0: 0 detection of memory transition (interrupt controller or bad memory) and recovery from video memory check; The descriptor table will be ready soon. System plug-in board selection failed.

42 Enter the setting display window. Descriptor table is ready; The virtual memory test will be conducted soon. Extended CMOS RAM failure.

If you plug and play BIOS, serial port and parallel port are initialized. Enter the virtual mode; Interrupt is about to be executed for diagnostic mode. .

44. The interrupt has been realized (for example, the diagnostic switch has been turned on; The data is about to be initially prepared to check that there is a 0: 0 rotation in the memory. ) BIOS interrupt to initialize.

Initialize the math coprocessor. The data has been preliminarily prepared; It is about to check that the memory is around 0: 0 to find out the size of the system memory. .

46. The test memory has been returned; After calculating the memory size, the page will be written to test the memory. Check the ROM version of the ROM.

47. Try to write a page in the extended memory; That is, write the basic 640K memory into the page. .

48. Basic memory has been written into the page; Memory above 1MB will be determined soon. Video detection, CMOS reconfiguration.

49. Find out the memory below 1BM and check it; Memory above 1MB will be determined soon. .

4A。 Check the memory above 1MB; The BIOS ROM data area will be checked. Initialize the video.

4b。 After checking the data area of the BIOS ROM, < < ESC > > will be checked, and the memory above 1MB will be cleared for soft reset. .

4C。 Clear the memory above 1MB (soft reset). Clear the memory above 1MB as soon as possible. Screen video BIOS ROM. .

In 4D, the memory above 1MB has been cleared (soft reset); Will save the size of memory. .

4e if an error is detected; Display an error message on the display screen and wait for the customer to press < f 1 > to continue. Start memory test: (no soft reset); The first test of 64K memory will be shown soon. Display copyright information.

4F Read and write software and hard disk data for DOS boot. Start to display the size of the memory, and the tested memory will be updated; Serial and random access memory tests will be conducted. .

50 Save the CMOS value of the current BIOS monitoring time zone into CMOS. Complete the memory test below 1MB; I.e. the size of the high-speed memory for relocation and masking. Send CPU type and speed to the screen.

5 1. Test the memory above 1MB. .

All ISAROMs are initialized, and finally PCI is assigned IRQ number. The memory test above 1MB has been completed; I will return to the real address mode. Enter the keyboard test.

If it is not a plug-and-play BIOS, initialize the serial port and parallel port and set the time value. Saving the size of CPU registers and memory will enter the real address mode. .

54. Successfully open the physical address mode; Registers saved when ready to shut down will be restored. Scan "keystroke"

55. The register has been restored, and the address line of gate A-20 will be disabled. .

56. The address line of A-20 was successfully deactivated; The BIOS ROM data area will be checked. The keyboard test is over.

57. The 57.BIOS ROM data area is checked by half; Go ahead. .

58. The data area of BIOS ROM is checked; Discovery < < ESC > > information will be cleared. Non-asserted interrupt test.

59.< < ESC > > information has been cleared; The information has been displayed; Testing of DMA and interrupt controller is about to begin. .

5A .. Press "F2" key to set the display.

5B .. Test the basic memory address.

5C .. Test 640K basic memory.

Set the virus protection function of hard disk boot sector. Pass the test of DMA page register; The video memory is about to be checked. Test the extended memory.

6 1 Display the system configuration table. Video memory check completed; The basic register of DMA # 1 will be tested soon. .

Start system boot with interrupt 19H. Pass the test of DMA # 1 basic register; DMA # 2 register will be tested soon. Test the extended memory address line.

63. Pass the test of DMA # 2 basic register; The BIOS ROM data area will be checked. .

64. The 64.BIOS ROM data area has been checked halfway, so continue. .

65.BIOS ROM data area check is over; DMA devices 1 and 2 will be programmed. .

66. The programming of DMA devices 1 and 2 ends; 59 # interrupt controller will be used for initial preparation. The cache registry is optimized.

The preparatory work for 67.8259 has been completed; The keyboard test is about to begin. .

68 .. Make both external cache and CPU internal cache work.

6A .. Test and display the external cache value.

6C .. Show blocked content.

6E .. Displays the attachment configuration information.

70 .. The detected error code is sent to the screen for display.

72 .. Check the configuration for errors.

74 .. Test the real-time clock.

76 .. scanning keyboard error.

7A .. Lock the keyboard.

7C .. Set the hardware interrupt vector.

7E .. Test whether the math processor is installed.

80. The keyboard test has started, and the check keys are being cleared, and the keyboard will be restored soon. Turn off the programmable input/output device.

8 1. Find out the wrong key stuck in keyboard recovery; A test command for the keyboard control port will be issued soon. .

82. After the keyboard controller interface test, command bytes will be written, and the circular buffer will be preliminarily prepared. Detect and install the fixed RS232 interface (serial port).

83. The command byte has been written and the initial preparation of global data has been completed; Check whether there is a key lock. .

84. The lock key has been checked, and it is about to check whether the memory does not match CMOS. Detection and installation of fixed parallel port.

85. The memory size has been checked; Soft errors and passwords or bypass arrangements will be displayed soon. .

86. The password has been checked; Program before the bypass arrangement is about to happen. Reopen the programmable I/O device and detect whether there is a conflict between fixed I/Os.

87. Complete programming before arrangement; Programming of CMOS layout will be carried out. .

88. Restore clear screen from CMOS scheduler; The next programming will be completed soon. Initialize the BIOS data area.

89. Finish programming after finishing; The boot screen information will be displayed soon. .

8A。 Display the first screen information. Initialize the extended BIOS data area.

8B。 Displays the message that the main BIOS and video BIOS will be blocked soon. .

8C。 Successfully shielded the main and video BIOS, and will start the programming of any option after CMOS. Initialize floppy drive controller.

8D。 Optional programming has been arranged, and the next step is to check the sliding mouse and make preliminary preparations. .

8E。 When the mouse is detected, the initial preparation is completed; The hard disk and floppy disk will be reset soon. .

8F。 The floppy disk has been checked, and it will be prepared initially, and then it will be equipped with floppy disks. .

90. The floppy disk configuration is over; The existence of the hard disk will be tested. Hard disk controller initialization.

9 1. The hard disk existence test has ended; Then configure the hard disk. Initialization of local bus hard disk controller.

92. The hard disk configuration is completed; The data area of the BIOS ROM will be checked. Jump to user path 2.

93. The data area of BIOS ROM has been checked by half; Go ahead. .

94. After checking the data area of BIOS ROM, set the size of basic and extended memory. Turn off the A-20 address line.

95. Adjust the memory size according to mouse and hard disk support 47; The display memory is about to be checked. .

96. Restore after checking the displayed memory; C800: 0 Optional initial preparation before ROM control. The "ES segment" registry is cleared.

97. Before C800: 0 optional ROM control, complete any initial preparation, and then check and control the optional ROM. .

98. Complete the control of optional ROM; Any processing required immediately after the optional ROM resumes control. Find ROM selection.

99. Any initial preparation required after the completion of the optional ROM test; The data area of the timer to be established or the basic address of the printer. .

9A。 Set the basic address of timer and printer and then return to operation; That is, set the basic address of RS-232. Mask ROM selection.

9B。 Return after RS-232 basic address; The initial preparation for coprocessor testing will be carried out soon. .

9C。 The initial preparation required before the coprocessor test is completed; Then the coprocessor is initially prepared. Establish energy-saving management of power supply.

9D。 The coprocessor makes initial preparation, that is, any initial preparation after the coprocessor test. .

9E。 After the initial preparation of the coprocessor is completed, the extended keyboard, keyboard identifier and digital lock will be checked. Turn on the hardware interrupt.

9F。 The extended keyboard has been checked, the identification mark has been set, and the digital lock has been opened or closed, and the keyboard identification command will be issued. .

A0, issuing a keyboard recognition command; Keyboard recognition sign will be restored soon. Set the time and date.

A 1。 Keyboard identification mark recovery; Then the cache is tested. .

A2。 Cache test completed; Any soft errors will show up soon. Check the keyboard lock.

A3。 Display soft errors; The speed of keyboard attack is about to be set. .

A4。 Adjust the hit rate of the keyboard, and the waiting state of the memory will be established soon. Initialization of keyboard repetition input rate.

A5。 The memory waits for the state to be completed; Then the screen will be cleared. .

A6。 The screen has been cleared; Parity and unmasked interrupts are about to begin. .

A7。 Enable non-maskable interrupts and parity; Any initial preparation required to control the optional ROM at E000: 0 will be completed soon. .

A8。 The control ROM completes the initial preparation before E000: 0, and then controls any initial preparation required after E000: 0. Clear the "F2" key prompt.

A9。 Return from controlling E000:0 rom, that is, make any necessary initial preparation after controlling E000:0 optional ROM. .

AA。 E000: 0 After controlling the optional ROM, the initial preparation is completed; The configuration of the system will be displayed. Scan "F2" keystroke.

Alternating current ... input settings.

Automatic exposure device .. Clear the power-on self-test sign.

B0 .. Check for non-critical errors.

B2 .. POST is complete and ready to boot to the operating system.

B4 .. The buzzer is ringing.

B6 .. Check the password settings (optional).

B8 .. Clear all description tables.

BC .. Clear the check value.

The default value of BE program enters the control chip, which conforms to the modulation binary default value table. . Clear the screen (optional).

BF test CMOS settings. Detect virus and prompt data backup.

C0 Initializes the cache. Try to boot with interrupt 19.

C 1 memory self-test. . Look for the "55" and "AA" marks in the boot sector.