The codes and meanings of the computer motherboard fault diagnosis card are as follows:

00 ? The configuration of the system has been displayed; The controller INT 19 will be started and loaded.

0 1 processor test 1, and handle state verification. If the test fails, the loop is infinite. The test of processor registers is about to begin, and unmasked interrupts are about to be disabled. The CPU register test is in progress or failed.

Determine the type of diagnosis (normal or manufacturing). If the keyboard buffer contains data, it will be invalid. Disable non-maskable interrupts; Start with procrastination. CMOS writing and reading is in progress or has failed.

Clear the 8042 keyboard controller and issue the TEST-KBRD command (AAH). Start-up delay completed. ROM B 10S check the parts or faults in progress.

Reset the 8042 keyboard controller and verify TESTKBRD. The keyboard controller is reset for power-on test. The test of the programmable interval timer is in progress or fails.

If the manufacturing test 1 to 5 is repeated continuously, the 8042 control state can be obtained. Confirm that soft reset is powered on; Is about to begin. DMA initial preparation is in progress or failed.

Make initial preparations for circuit chips, disable video, parity and DMA circuit chips, and clear DMA circuit chips, all page registers and CMOS stop bytes.

07 processor test 2, verify the operation of CPU registers. ROM BIOS checksum is normal, keyboard buffer has been emptied, and BAT (basic guarantee test) command is issued to the keyboard. Insignificant/meaningless

Make initial preparation for CMOS timer and update the timer cycle normally. The BAT command has been downloaded to the keyboard, and the BAT command will be written soon. RAM update check is in progress or has failed.

The sum of EPROM check must be equal to zero before passing. Verify the basic guarantee test of the keyboard, and then verify the keyboard command bytes. The first 64K memory test is in progress.

Make preliminary preparations for the video interface. Issue keyboard command byte code and write command byte data. The first 64K RAM chip or data line fails and shifts.

Test 8254 channel 0. When the command byte of keyboard controller is written, the locking and unlocking commands of pins 23 and 24 will be issued. The first 64K RAM parity logic failed.

Test channel 8054 1. Keyboard controller pins 23 and 24 have been locked and unlocked; NOP command has been issued. The address line of the first 64K RAM failed.

0D 1。 Check whether the CPU speed matches the system clock. 2. Check whether the programmed value of the control chip meets the initial setting. 3. Video channel test. If you fail, honk the horn. NOP command has been processed; Then test the CMOS stop register. The parity check of the first 64K RAM failed.

Test CMOS power-off bytes. CMOS stops register reading and writing test; CMOS checksum will be calculated. Initial cargo input/output port address.

0F test extended CMOS. The calculated CMOS checksum is written into the diagnostic byte; CMOS begins initial preparation.

10 test DMA channel 0. CMOS has made preliminary preparations, and the date and time of CMOS status register are about to be prepared. The first 64K RAM bit 0 failed.

Test DMA channel 1. COMS status register is initially prepared to disable DMA and interrupt controller. The first 64K RAM bit 1 failed.

12 test DMA page register. Deactivate DMA controller 1 and interrupt controller 1 and 2; That is, the video display and port B are initially prepared. The second bit of the first 64K RAM failed.

13 Test the 847 1 keyboard controller interface. Video surveillance has been disabled, and port B has been preliminarily prepared; The automatic detection of circuit chip initialization memory is about to begin. The third bit of the first 64K RAM failed.

14 Test the memory update trigger circuit. Complete the automatic detection of the circuit chip initialization memory; The 8254 timer test is about to begin. The 4th bit of the first 64K RAM failed.

15 Test the system memory starting with 64K. Channel 2 timer has been tested halfway; The 8254 Channel 2 timer is about to complete the test. The 5th bit of the first 64K RAM failed.

16 Establish the interrupt vector table used by 8259. End of channel 2 timer test; The 8254 channel 1 timer is about to complete the test. The 6th bit of the first 64K RAM failed.

17 aligns the video input and output, and enables the video BIOS if it is installed. 1 End of channel timer test; Channel 0 of 8254 is about to complete the test. The 7th bit of the first 64K RAM failed.

18 test memory. If the selected video BIOS passes, it can be bypassed. End of channel 0 timer test; Updating memory is about to begin. The first 64K RAM bit 8 failed.

Mask bit of interrupt controller (8259) of 19 test channel 1. The update of the memory has started, and then the update of the memory will be completed. The 9th bit of the first 64K RAM failed.

1A Test the mask bit of the interrupt controller (8259) in channel 2. The memory update line is being triggered, and the on-off time of 15 microseconds is about to be checked. The first 64K RAM bit 10 failed.

1B measure the charge of CMOS battery. Complete the memory refresh time test of 30 microseconds; The basic 64K memory test is about to begin. The first 64K RAM failed at 1 1.

1C test COMS checksum. Meaningless. The first 64K RAM bit 12 failed.

1D sets the configuration of COMS. Meaningless. The first 64K RAM bit 13 failed.

1E measures the size of system memory, and compares the objective existence with COMS value. Meaningless. The first 64K RAM bit 14 failed.

1F tests 64K memory with a maximum of 640K. Meaningless. The first 64K RAM bit 15 failed.

Measure the fixed 8259 interrupt bit. Start the basic 64K memory test; The address line is about to be tested. The slave DMA register test is in progress or failed.

2 1 Maintain NMI bits (parity of input and output channels). Pass the address line test; Parity is about to be triggered. The main DMA register test is in progress or failed.

Test the interrupt function of 8259. End trigger parity; The serial data read-write test will begin. The host interrupt mask register is running or faulty.

23 test protection mode, 8086 virtual mode and 8 186 page mode. The basic 64K serial data reading and writing test is normal; Any adjustment before the interrupt vector is initialized will begin. The slave interrupt mask register test is in progress or failed.

Measure the extended memory above 1Mb. Any adjustment before vector initialization is completed, and the initial preparation of interrupt vector is about to begin. Set the ES segment address register registry to the high end of the memory.

Test all memory except the first 64K. Complete that initial preparation of the interrupt vector; For the rotating arm, the I/O port of 8042 will be read intermittently. Loading interrupt vector is in progress or failed.

26 exceptions to test protection methods. Read and write the input and output ports of 8042; The global data was originally prepared for the intermittent start of rotation. Open the A20 address line; Make it participate in addressing.

Determine the control or mask RAM of the cache. The initial preparation of all 1 data is completed; Any initial preparation after the interrupt vector will follow. Keyboard controller test is in progress or failed.

Determine the cache controller or dedicated 8042 keyboard controller. Initial preparation after completing the interrupt vector; We are about to adjust the monochrome wide style. CMOS power supply fault checksum calculation is in progress.

The monochrome mode has been adjusted, and the color mode is about to be adjusted. The validity check of CMOS configuration is in progress.

2A Make preliminary preparations for the keyboard controller. The color mode has been set, and the trigger parity before the ROM test is about to be carried out. Clear 64K basic memory.

2B Make initial preparations for disk drives and controllers. Triggering the end of parity check; Any adjustments required before checking the optional video ROM will be controlled. Screen memory test is in progress or failed.

2C Check the serial port and make initial preparations. Complete the processing before the video ROM control; You will view and control the optional video ROM. Initial screen preparation is in progress or there is a failure.

2D Check the parallel serial port and make preliminary preparations. Complete optional video ROM control, that is, control of any other processing after video ROM recovery control. The screen retrace test is in progress or has failed.

2E Make initial preparations for disk drives and controllers. Processing after resuming video ROM control; If EGAVGA cannot be found, you need to test the reading and writing of the display memory. Checking video ROM.

2F Detect the math coprocessor and make preliminary preparations. No EGAVGA was found; Shows that the memory read-write test is about to begin. Meaningless.

Establish basic memory and expand memory. Pass the display memory reading and writing test; Scanning inspection is about to take place. I think the screen is working properly.

3 1 detect the ROM selection from C8000 to EFFF0 to prepare for life. The display memory read-write test failed, and another display memory read-write test will be conducted soon. Monochrome display can work.

32. Program the IO chips such as COMLTPFDD sound equipment on the motherboard to make them suitable for the set values. Pass the read-write test of another display memory; Another kind of monitor scanning inspection is coming soon. The color display (40 columns) can work.

33 video surveillance inspection is over; The type of monitor will be checked by adjusting the switch and the actual card. The color display (80 columns) can work.

34 Verified display adapter; Then the display mode will be adjusted. The timer tick interrupt test is in progress or has a fault.

35. Complete the setting of display mode; The data area of the BIOS ROM will be checked.

Note: this code is only applicable to PCIISA dual-purpose and PCI stand-alone models.

Extended data

Fast lookup table for indicator function of computer motherboard fault diagnosis card

CLK bus clock, whether ISA or PCI, should always be on as long as it is empty (no CPU, etc.). ) is turned on, otherwise the CLK signal will be bad.

When the BIOS basic input and output motherboard is running, it will flash if there is a reading operation to the BIOS.

The IRDY master device will flash only when it is ready to receive the IRDY signal, otherwise it will not light up.

OSC oscillates the main vibration signal of ISA tank, and the power supply on the empty disk should always be on, otherwise the vibration will stop.

This light flashes only when there is a cyclic frame signal in the PCI slot of the frame period, and it is always on at ordinary times.

It is normal for RST to open after reset or close for half a second after pressing the reset switch. If it is not turned off, it is often because the reset pin on the motherboard is connected with the acceleration switch or the reset circuit is broken.

The blank board of 12V power supply should always be on, otherwise there is no such voltage or the motherboard is short-circuited.

-12V power supply should be turned on all the time, otherwise there will be no such voltage or the motherboard will be short-circuited.

The blank board of 5V power supply should always be on, otherwise there is no such voltage or the motherboard is short-circuited.

The blank board of -5V power supply should always be on, otherwise there will be no such voltage or the motherboard will be short-circuited. (Only ISA slot has this voltage)

3V3 Power Supply This is the unique 3.3V voltage of PCI slot, which should always be turned on when the motherboard is powered on. Some motherboards with PCI slots will not light up without this voltage.

References:

Baidu Encyclopedia-Computer Motherboard Fault Diagnosis Card