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We are going to do a course design on digital electronic clocks, can you help me?
Design of a digital electronic clock (composed of digital ICs) I. Design Objectives

1. Familiarize yourself with the pin-out arrangement of integrated circuits.

2. To master the logic function of each chip and how to use it.

3. To understand the breadboard structure and its wiring method.

4. Understand the composition and working principle of digital clock.

5. Familiarize with the design and production of digital clocks. Second, the design requirements

1. design indicators time to 24 hours as a cycle; display hours, minutes, seconds; have a calibration function, respectively, the hours and minutes can be individually calibrated, so that it is corrected to the standard time; the timing process has a chime function, when the time reaches the full 5 seconds before the beeping chime; in order to ensure that the timing of the stability and accuracy of the crystal oscillator to provide the watch hand time reference signal. 2. design requirements to draw the circuit schematic diagram

3. design requirements to draw the circuit schematic diagram

4. Design requirements to draw the circuit schematic (or simulation circuit diagram); components and parameters selection; circuit simulation and debugging; PCB file generation and printout.

3. Production requirements Self-assembly and debugging, and be able to find problems and solve problems.

4. Write a design report Write the whole process of design and production, with relevant information and drawings, with experience.

Three, the design principle and its block diagram

1. The composition of the digital clock

The digital clock is actually a counting circuit that counts the standard frequency (1HZ). Because the counting of the starting time is not possible with the standard time (such as Beijing time), it is necessary to add a calibration circuit on the circuit, while the standard 1HZ time signal must be accurate and stable. Usually use a quartz crystal oscillator circuit to form a digital clock. Figure 3-1 shows the general composition of the digital clock block diagram.

Figure 3-1 Block Diagram of a Digital Clock

(1) Crystal Oscillator Circuit

The crystal oscillator circuit provides the digital clock with a stable and accurate 32768Hz square wave signal, which ensures that the digital clock is accurate and stable. The crystal oscillator circuit is used in both analog and digital clocks.

(2) Frequency Divider Circuit

The frequency divider circuit divides the 32768Hz high-frequency square wave signal by 32,768 ( ) times to obtain a 1Hz square wave signal for the second counter to count. The frequency divider is actually a counter.

3) Time Counter Circuit

The time counter circuit consists of second bit and second ten-bit counter, minute bit and minute ten-bit counter, and hour bit and hour ten-bit counter circuit, in which the second bit and second ten-bit counter, minute bit and minute ten-bit counter are 60-bit counters, and according to the design requirements, the hour bit and hour ten-bit counter are 12-bit counters.

(4) Decoder Driver Circuit

The decoder driver circuit converts the 8421BCD code output from the counter into the logic state required by the digital tube, and provides enough working current to ensure the normal operation of the digital tube.

(5) digital tube

Digital tube usually have a light-emitting diode (LED) digital tube and liquid crystal (LCD) digital tube, this design provides the LED digital tube.

2. The working principle of the digital clock

1) Crystal oscillator circuit

The crystal oscillator is the core of the digital clock, which ensures that the clock is accurate and stable.

Figure 3-2 shows a digital crystal oscillator circuit with a square wave output through a CMOS non-gate. In this circuit, the CMOS non-gate U1 is used to form a crystal oscillator circuit with crystals, capacitors, and resistors, and U2 is used to realize the shaping function, which converts the oscillator's output waveform from a sinusoidal waveform to a more ideal square wave. The output feedback resistor R1 provides bias for the non-gate to operate in the amplification region, i.e., the non-gate functions as a high-gain inverting amplifier. Capacitors C1 and C2 form a resonant network with the crystal to accomplish the function of controlling the oscillation frequency, and at the same time provide a 180-degree phase shift, thus forming a positive feedback network with the non-gate to realize the function of the oscillator. As the crystal has high frequency stability and accuracy, thus ensuring the stability and accuracy of the output frequency.

The frequency of crystal XTAL is selected as 32768 HZ. This component is designed for digital clock circuits, and its lower frequency is conducive to reducing the number of crossover stages.

From the relevant manual, can be found in C1, C2 are 30pF. When the requirements of frequency accuracy and stability is higher, but also access to the correction capacitor and take temperature compensation measures.

Because the input impedance of CMOS circuits is extremely high, the feedback resistor R1 can be selected as 10MΩ. Higher feedback resistance is conducive to improving the stability of the oscillation frequency.

The non-gate circuit can be 74HC00.

Figure 3-2 COMS Crystal Oscillator

2) Frequency Divider Circuit

Usually, the crystal oscillator of a digital clock has a high output frequency, and in order to get the input of the second signal at 1Hz, the output signal of the oscillator needs to be divided into frequencies.

The circuit that usually realizes the frequency divider is a counter circuit, which is usually realized by using a multi-stage binary counter. For example, the oscillating signal of 32768Hz will be divided into 1HZ frequency division multiple of 32768 (215), that is, the realization of the frequency division function of the counter is equivalent to 15-pole binary counter. Commonly used binary counter 74HC393 and so on.

The CD4060 is used in this experiment to form the frequency division circuit. the CD4060 can be realized in the digital integrated circuits of the highest number of frequency division, and the CD4060 also contains the oscillation circuit required for the non-gate, the use of more convenient.

CD4060 counts for 14 levels of binary counter, can be 32768HZ signal frequency division of 2HZ, its internal block diagram shown in Figure 3-3, from the figure can be seen, the CD4060 clock inputs two series connected to the non-gate, so you can directly realize the function of oscillation and frequency division.

Figure 3-3 Internal Block Diagram of CD4046

3) Time Counting Unit

The time counting unit consists of several parts, such as time counting, minute counting and second counting.

The time counting unit is generally a 12-digit counter, whose output is in the form of a two-digit 8421BCD code; the minute counting and second counting unit is a 60-digit counter, whose output is also a 8421BCD code.

Generally use the 10 counter 74HC390 to realize the counting function of the time counting unit. In order to reduce the number of devices used, optional 74HC390, its internal logic block diagram shown in Figure 2.3. The device is a dual 2-5-10 asynchronous counter, and each counter provides an asynchronous clear terminal (active high).

Figure 3-4 74HC390(1/2) Internal Logic Block Diagram

Seconds single-digit counter is a 10-bit counter, which does not require any conversion, and only needs to connect QA to CPB (active on falling edge), which is connected to the 1HZ seconds input signal, and Q3 can be used as an upward rounding signal to connect to CPA in the 10-digit counting unit.

The second ten-bit counter unit is a hexadecimal counter, which requires conversion. The circuit connection method for converting a 10-bit counter to a 6-bit counter is shown in FIGS. 3-5, in which Q2 can be connected as an upward feed signal to the CPA of the sub-division counting unit.

Figure 3-5 Conversion circuit of decimal to hexadecimal counter

The circuit structure of the single-digit and ten-digit counter units is identical to that of the single-digit and ten-digit counter units, except that Q3 of the single-digit counter unit should be connected to the CPA of the ten-digit counter unit as an upward feed signal. The Q2 of the minute-ten counter is connected to the CPA of the hour counter as an upward feed signal.

The circuit structure of the time-digit counting unit is still the same as that of the second or digit counting unit, but the whole time-counting unit is required to be a 12-bit counter, which is not an integer multiple of 10, and therefore needs to be merged with the digit counting unit and the ten-digit counting unit as a whole in order to carry out the 12-bit conversion. Utilizing a piece of 74HC390 to realize the 12-base counting function of the circuit is shown in Figure 3-6.

In addition, Figure 3-6 shows the circuit, the remaining -2 counting unit, can be used as a frequency divider 2HZ output signal into 1HZ signal.

Figure 3-6 12-bit counter circuit

4) decoder driver and display unit

The counter realizes the totalization of time in the form of 8421BCD code output, the choice of the display decoder circuit will be the counter's output digital digital converter for digital display devices need to be the output of the logic and a certain amount of current, the choice of CD4511 as the display decoder circuit, the choice of the LED digital tube as the display unit. Selection of LED digital tube as the display unit circuit.

5) calibration power supply circuit

When the power supply is reconnected or when the time error is required to correct the time. Usually, the method of correcting time is: first cut off the normal counting path, and then artificial out of the trigger counting or higher frequency square wave signal added to the input of the counting unit needs to be corrected, corrected, and then transferred to the normal timing state can be.

According to the requirement, the digital clock should have the function of calibration and time correction, therefore, the direct counting path should be truncated for the sub-bit and the time bit, and the normal timing signal and the correction signal can be switched at any time to access the circuit. Figure 3-7 shows that the basic RS trigger with the calibration circuit,

Figure 3-7 with the jitter circuit correction circuit

6) whole point chime circuit

General clock should have the whole point of the chime circuit function, that is, in the time of the whole point of time in a few seconds before the time, digital clocks will be automatically chiming to show that the reminder. Its role is to send a continuous or rhythmic audio sound waves, more complex can also be real-time voice prompts.

According to the requirements, the circuit should be 10 seconds before the whole point to start the whole point of the time, that is, when the time in the period of 59 minutes and 50 seconds to 59 minutes and 59 seconds, the chime circuit chimes the time control signal. Reporting circuit selected 74HC30, selected buzzer for the electro-acoustic device.

Four, components

1. equipment required in the experiment: 5V power supply. Breadboard 1. Oscilloscope. Multimeter. Tweezers 1. Scissors 1. Network cable 2 meters / person.

***Yin eight-segment digital tube 6. CD4511 integrated block 6 pieces. CD4060 integrated block 1 piece. 74HC390 integrated block 3 pieces.

74HC51 integrated block 1. 74HC00 integrated block 5. 74HC30 integrated block 1. 10MΩ resistance 5.

500Ω resistor 14 pcs. 30p capacitor 2 pcs. 32.768k clock crystal 1 pc. Buzzer.