1, because the memory address number of 1024K*32 bits is 1024K, which consists of 5 12 rows and 2048 columns, and the DRAM chip is refreshed by rows, so the refresh address is 9 bits (because the 9th power of 2 = 512) There are 2048 columns in a row.

2. The refresh interval of cells should not exceed 8ms, that is, all rows should be refreshed within 8ms (otherwise the charge will leak). It takes one refresh cycle to refresh a row, so it takes 5 12 refresh cycles to refresh 5 12 rows.